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Host Programmer Model
Table 6-13. DSP-Side Registers After Reset
Reset Type
Register
Register
Name
HCR
HPCR
HSR
HBAR
HDDR
HDR
HRX
HTX
Data
All bits
All bits
HF[1–0]
HCP
HTDE
HRDF
BA[10–3]
DR[15–0]
D[15–0]
HRX [23–0]
HTX [23–0]
HW
Reset
0
0
0
0
1
0
$80
0
—
empty
empty
SW
Reset
0
0
0
0
1
0
$80
0
—
empty
empty
IR
Reset
—
—
—
0
1
0
—
—
—
empty
empty
ST
Reset
—
—
—
0
1
0
—
—
—
empty
empty
Note:
A long dash (—) denotes that the bit value is not affected by the specified reset.
6.7 Host Programmer Model
The HI08 provides a simple, high-speed interface to a host processor. To the host bus, the HI08
appears to be eight byte-wide registers. Separate transmit and receive data paths are
double-buffered to allow the DSP core and host processor to transfer data efficiently at high
speed. The host can access the HI08 asynchronously using polling techniques or interrupt-based
techniques. The HI08 appears to the host processor as a memory-mapped peripheral occupying
eight bytes in the host processor address space. (See Table 6-14 .)
The eight HI08 registers include the following:
A control register (ICR), on page 6-22
A status register (ISR), on page 6-25
Three data registers (RXH/TXH, RXM/TXM, and RXL/TXL), on page 6-27
Two vector registers (CVR and IVR), on page 6-24 and page 6-27
To transfer data between itself and the HI08, the host processor bus performs the following steps:
1.
2.
3.
Asserts the HI08 address and strobes to select the register to be read or written. (Chip
select in non-multiplexed mode, the address strobe in multiplexed mode.)
Selects the direction of the data transfer. If it is writing, the host processor places the
data on the bus. Otherwise, the HI08 places the data on the bus.
Strobes the data transfer.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
6-21
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